1. Field
The present description relates to dynamically controlling a pre-charge level in a semiconductor device, and in particular to applying at least two different pre-charge levels to reduce gate leakage and power consumption.
2. Background
Semiconductor devices, such as transistors, diodes and capacitors experience current leakage. The leakage can occur in gates and other components of semiconductor devices. The leaked current generates heat so that power consumption and cooling requirements are increased. In some circumstances, current leakage can diminish signal fidelity or capacity. The leakage current can also affect other nearby devices. As a result, semiconductor systems, such as microprocessors, CPUs (Central Processing Units), ASICs (Application Specific Integrated Circuits), FPGAs (Field Programmable Gate Arrays), DSPs (Digital Signal Processors), and memory arrays, among others are often designed with an intent to reduce leakage and to guide leakage current away from sensitive portions of the semiconductor circuitry.
In memory arrays, there is significant leakage at bit-line gates and word-line gates. Many memory cell designs require constant power to maintain a memory state and to allow the memory to be read or written to. The leakage current increases the power consumption of the memory array whether or not the memory is being used. In the design of microprocessors, this leakage current has been considered to be insignificant and has been managed primarily by protecting sensitive devices from it. However, as the amount of cache memory in microprocessors increases and as the size of the transistors and other devices is reduced, the amount of leakage current in a microprocessor is increased. Similarly, the power consumed by leakage current in any large memory array increases as the number of memory cells and the cell density is increased.